1. Field of the Invention
The invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to a method for forming a metal-oxide-semiconductor (MOS) transistor having a metal gate.
2. Description of the Related Art
A MOS transistor including stacked films and layers made of metal, oxide, and semiconductor is nowadays the most important device in the VLSI fabrication process, wherein the most popular semiconductor material used in a modern MOS transistor is silicon. Even though aluminum is used to form metal layers in most semiconductor devices, it cannot be used to form metal layers in a MOS transistor because aluminum causes fabrication problems in a high temperature environment. On the other hand, because most metals other than aluminum have a poor adhesion to silicon oxide, polysilicon has an excellent adhesion to silicon oxide and is currently used to replace metals in semiconductor fabrication process. However, using polysilicon to replace metal leads to a problem that the resistance of polysilicon, or even doped polysilicon, is too high to be used as metal in a MOS transistor. A conventional resolution to the forgoing problem is to form an extra metal silicide layer on the polysilicon to reduce the resistance of the polycide gate.
When the integration of an integrated circuit increases, the sheet resistance of the drain and source of the metal oxide semiconductor (MOS) transistor increases until the sheet resistance matches the channel resistance of the MOS transistor. To bring down the sheet resistance of the drain and the source of the MOS transistor and to ensure the integrity of a shallow junction between metal and MOS, salicide has been increasingly applied to the fabricating procedure.
For forming a conventional MOS transistor having salicide layer, the application of salicide is used to form a metal silicide layer on a polysilicon gate of the MOS transistor to decrease resistance of the gate of the MOS transistor.
FIG. 1 is a cross-sectional view showing a conventional MOS transistor. An isolating region 102 is formed on a substrate 100 to separate active regions of the substrate 100. A gate oxide layer 104 and a polysilicon gate 106 are formed on the substrate 100. Source/drain regions are formed in the substrate 100. A channel region of a MOS transistor is thus determined. The source/drain region of a conventional MOS transistor is normally replaced with a lightly doped drain (LDD) region to eliminate the hot carrier effect caused by the short channel effect. To form a MOS transistor with the LDD region normally comprises forming lightly doped regions 108 in the substrate 100. A spacer 110 is formed on the sidewalls of the polysilicon gate 106. Heavily doped regions as source/drain regions 112 are formed in the substrate 100 using the polysilicon gate 106 and the spacer 110 as a mask.
In order to reduce the resistance of the polysilicon gate 106 and the source/drain regions 112, metal silicide 118 and 120 are formed over the polysilicon gate 106 and the source/drain regions 112 by performing a salicide process. However, when the foregoing fabrication process is applied to a semiconductor device whose design rule is at a deep submicron level, a lower resistance and a shallower junction of a MOS transistor than those of the conventional MOS transistor are required. The salicide process has problems when forming a MOS transistor with lower resistance and a shallower junction. One of the problems is that salicide formed within the source/drain regions directly contacts the substrate in the shallower junction. Devices having a MOS transistor such as described above suffer failure from shorts between the substrate and the salicide.